As technology advances, new semiconductor memory devices have been required to store more information and to communicate that information more quickly. A dual-port memory structure is one such memory device that provides data in an efficient manner desired by current data processing systems. In a dual port memory, two ports are implemented so that the contents of the memory may be concurrently accessed from two different sources. An example of such a dual port memory is illustrated in FIG. 1.
In the dual port memory cell of FIG. 1, transistors 106, 108, 110, and 112 form a latch for storing data within the memory cell. In contrast, transistors 104, 102, 114, and 116 are pass devices that allow data to be stored within and read from the memory cell. Through the selective enabling of the "latch" transistor and the "pass" transistors, data is stored within and read from the dual-port memory cell. However, the use of multiple pass devices within this memory cell may result in a "read disturb" problem, whereby the data in the memory cell is incorrectly read due to improper current distribution when the cell is read. To explain such "read disturb" problems in greater detail, a detailed explanation of operation of a dual-port memory cell will now be provided.
Assume in the memory cell of FIG. 1 that node 1, N1, has a logic one value thereon. Conversely, node 0 (N0) has a logic zero value thereon. Furthermore, assume that nodes BL.sub.0, BL.sub.0 , BL.sub.1, and BL.sub.1 , are all precharged to a logic high value when the P1WL and the P2WL signals are a logic low value. Subsequently, when the P2WL signal is asserted, transistor 116 forms a pass device which has a logic low on one side and a logic high value on the other side. When a pass device, such as transistor 116 is enabled by a wordline (Q2 P2WL, in this example), the pass device is operating a saturation region. Note that transistor 112 is in a linear mode of operation when either wordline is enabled ("turned on") because V.sub.DS =0 and V.sub.DS &lt; V.sub.GS -V.sub.T. When such a differential exists, transistor 112 in the linear is required to transfer the same current as transistor 116 in the saturation mode. If transistor 112 is the same size (w/l (width/length) ratio) as transistor 116, transistor 112 will not be able to "sink" all the current through node N0 without node N0 rising significantly above a ground reference voltage. As node N0 rises above ground to a threshold voltage, Vtn, above the ground reference voltage, transistor 108 is enabled to conduct current. As transistor 108 is enabled to conduct current, the two inverters will contend with one another. If node N0 continues to rise, the latch in the cross-coupled cell will eventually flip its logic state, and Node 0 will become a logic one value. Therefore, if transistor 112 cannot sink the same current that transistor 116 is sourcing, the voltage level on node N0 will become too high, the contents of the latch formed by transistors 106, 108, 110, and 112 will be disturbed, and the contents of the latch will switch to an opposite logic state, referred to as a read disturb.
To compensate for such potential disturbances, designers of memory systems, typically calculate a critical beta ratio to ensure that the memory cell will continue to operate properly, even during a read operation. This critical ratio is a ratio between the device size (w/l) of a latch device (such as transistor 112) and a pass device (such as transistor 116). Typically, the latch device must have a larger size (w/l) than the pass device. The beta ratio is defined as an effective width (W.sub.eff) over an effective length (L.sub.eff) of a transistor 112 divided by of effective width (W.sub.eff) over effective length (L.sub.eff) of transistor 116 or: ##EQU1##
In the case of a single-port memory cell, the will ratio of the latch device should be at least two times the w/l ratio of the pass device. By making this critical ratio approximately two, a circuit designer is assured that the pass device, transistor 112, while operating in a low VDS region is able to sink the current from the latch device when it is operating in a high VDS region.
To further complicate matters, in a dual port memory cell, two pass devices can potentially be driving concurrently current to a node (such as node N0). When this second pass device is used, a beta ratio between the pass devices and the latch devices must be increased by two times since there will be twice as much current as there are twice as many pass devices. Such an increased beta ratio is reflected in increased circuit area requirements which, in turn, increase the costs associated with manufacturing the circuit.
Therefore, a need exists for a method of accessing dual port memories which reduces an amount of circuit area requirements, while maintaining the functionality typically associated with such dual port memories.